DocumentCode :
1967494
Title :
A Cluster-Based Core Protection Technique for Networks-on-Chip
Author :
Latif, Khalid ; Rahmani, Amir-Mohammad ; Liljeberg, Pasi ; Tenhunen, Hannu ; Seceleanu, Tiberiu
Author_Institution :
Finland Turku Centre for Comput. Sci. (TUCS), Univ. of Turku, Turku, Finland
fYear :
2012
fDate :
16-20 July 2012
Firstpage :
360
Lastpage :
361
Abstract :
Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead.
Keywords :
failure analysis; fault tolerant computing; network routing; network-on-chip; NoC systems; PVS architecture; area overhead; average packet latency reduction; cluster-based processing core protection technique; data packet reception; data packet transmission; faulty node processing core; network level faults; network-on-chip; partial virtual channel sharing architecture; performance enhancement; routers; Computer architecture; Fault detection; Fault tolerance; Fault tolerant systems; Multiplexing; Routing; Fault Tolerance; Networks-on-Chip; Virtual Channel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Software and Applications Conference (COMPSAC), 2012 IEEE 36th Annual
Conference_Location :
Izmir
ISSN :
0730-3157
Print_ISBN :
978-1-4673-1990-4
Electronic_ISBN :
0730-3157
Type :
conf
DOI :
10.1109/COMPSAC.2012.55
Filename :
6340177
Link To Document :
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