A mixed-signal DFE/FFE receiver for 100Base-TX applications

Several 100Base-TX receivers have been built with DFE and FFE functions implemented in DSP. These implementations tend to be large in area and high in power. In addition, the large amount of digital logic switching at high speeds can lead to EMI issues. Finally, since a finite resolution must be chosen in a DSP implementation, noise immunity is reduced due to quantization noise. This chip uses mixed-signal techniques to implement the DFE and FFE functions of a 100BASE-TX receiver. The 100BASE-TX receiver uses a switched-capacitor, fixed coefficient FFE to cancel precursor ISI and create the timing function, a mixed-signal current-summing fully adaptive DFE to cancel post-cursor ISI, a fast offset cancellation tap to cancel baseline wander, and a coarse comparator to make decisions. Timing information, extracted from the received signal, is input to a digital signal processing (DSP) engine which emulates a second-order phase-locked loop (PLL) function. The function includes both proportional and integral representations of the timing information. A phase-interpolating PLL generates the recovered clock from the output of the DSP engine.