A 2 V 5.1-5.8 GHz image-reject receiver with wide dynamic range

A 5-6 GHz image-reject receiver IC implemented in 0.5 /spl mu/m 25 GHz silicon bipolar technology draws 20 mA from a 2 V supply. The image rejection obtainable with this IC is sufficient to eliminate the off-chip interstage RF filter in a heterodyne receiver, thereby simplifying packaging requirements and decreasing costs. The methods used here that make this design possible are: regenerative frequency doubling, I-Q phase error compensation and RF interstage coupling. Low-voltage circuit topologies are used throughout to minimize power consumption and ensure compatibility with deep sub-micron CMOS (baseband) ASICs operating from low-voltage supplies.