A 2.5 MSample/s multi-bit /spl Delta//spl Sigma/ CMOS ADC with 95 dB SNR

/spl Delta//spl Sigma/ A/D converters combine high resolution and high speed. A significant improvement in performance is achieved by employing a multi-bit quantizer. However, the linearity requirements for the DAC in the feedback loop are severe. To relax these requirements, dynamic element matching (DEM) techniques such as data weighted averaging (DWA) are used, converting noise and distortion introduced by the non-ideal DAC into a noise shaped error. These DEM techniques require an additional digital block in the feedback loop of the converter to scramble the used unity elements in each clock period. The delay introduced in the feedback loop by this block imposes a limit on the maximum clock frequency of the converter. Here, implementation of the DWA algorithm is optimized for high-speed converters, resulting in a 2.5MSample/s 16b A/D converter in a 0.65 /spl mu/m CMOS technology operating at 60 MHz clock speed.