• DocumentCode
    1967897
  • Title

    A 120 dB multi-bit SC audio DAC with second-order noise shaping

  • Author

    Xue-Mei Gong ; Gaalaas, E. ; Alexander, M. ; Hester, D. ; Walburger, E. ; Bian, J.

  • Author_Institution
    Cirrus Logic, Austin, TX, USA
  • fYear
    2000
  • fDate
    9-9 Feb. 2000
  • Firstpage
    344
  • Lastpage
    345
  • Abstract
    The 24 b consumer audio formats such as DVD-A make low-cost, high-performance audio converters essential. Multi-bit /spl Sigma//spl Delta/ modulators are the preferred choice for converters achieving high performance, especially in DACs. Compared with continuous-time, current mode DACs, a SC architecture provides significantly higher clock-jitter tolerance and eliminates inter-symbol interference. The performance of conventional 1 b SC DACs is limited by severe post-filtering needs and constrained signal swings due to poor modulator stability. The relaxed filtering needs and better modulator stability of a multi-bit approach make the multi-bit DAC an attractive alternative. However, nonlinearity caused by sampling element mismatch must be overcome to produce a low-distortion device. Second-order dynamic element matching (DEM) is used to address the nonlinearity issue. The second-order DEM technique used here is an improvement on the second-order data weighted averaging (2DWA) DEM technique reported previously. The DAC using this DEM achieves 100 dB THD and -120dB integrated noise over 20 kHz band. The 9.4 mm/sup 2/ chip is fabricated in a 0.35 /spl mu/m DPTM CMOS process. The analog part operates on a 5 V supply and the digital part operates at both 3.3 V and 5 V. The chip consumes <200 mW when the digital part operates at 3.3 V.
  • Keywords
    CMOS integrated circuits; audio signal processing; circuit stability; digital-analogue conversion; interference suppression; mixed analogue-digital integrated circuits; nonlinear distortion; switched capacitor networks; 0.35 micron; 20 kHz; 200 mW; 3.3 V; 5 V; DPTM CMOS process; DVD; ISI elimination; SC architecture; audio converters; clock-jitter tolerance; data weighted averaging; inter-symbol interference; low-distortion device; modulator stability; multi-bit /spl Sigma//spl Delta/ modulators; multi-bit SC audio DAC; nonlinearity; sampling element mismatch; second-order dynamic element matching; second-order noise shaping; Clocks; Filtering; Interference constraints; Interference elimination; Logic devices; Low pass filters; Noise shaping; Sampling methods; Stability; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-5853-8
  • Type

    conf

  • DOI
    10.1109/ISSCC.2000.839809
  • Filename
    839809