DAGAR: an automatic pipelined microarchitecture synthesis system

Author

Raj, Vijay K.

Author_Institution

Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA

fYear

1989

fDate

2-4 Oct 1989

Firstpage

428

Lastpage

431

Abstract

An automated microarchitecture synthesis system called DAGAR is presented. DAGAR takes as input a behavioral description of a digital system and outputs a microinstruction (MI) sequence and a data path. In microarchitectures synthesized by DAGAR the functional units (FUs) may take one or more clocks (i.e. MIs) to perform an operation. These are called multiclocked FUs. Additionally, if these FUs can accept new data while processing data from a previous MI, they are called pipelined FUs. The use of pipelined FUs is shown to decrease the number of FUs in the data path without a time penalty. Unlike other systems, DAGAR deals with the partitioning of a single FU into stages

Keywords

circuit layout CAD; DAGAR; automatic pipelined microarchitecture synthesis system; behavioral description; clocks; data path; digital system; functional units; input; microinstruction sequence; multiclocked FUs; outputs; partitioning; pipelined FUs; Clocks; Computer science; Design engineering; Digital systems; Microarchitecture; Pipeline processing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63402

Filename

63402