Title :
DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs
Author :
Yoshimura, R. ; Tan Boon Keat ; Ogawa, T. ; Hatanaka, S. ; Matsuoka, T. ; Taniguchi, K.
Author_Institution :
Dept. of Electron. & Inf. Syst., Osaka Univ., Japan
Abstract :
A new bus architecture is described which is suitable for a parallel processing system without complexity of interconnection, and also drastically reduces the I/O pin count, which is highly desirable for future gigascale integrated systems. The architecture is based on the direct sequence code division multiple access (DS-CDMA) technique.
Keywords :
VLSI; code division multiple access; integrated circuit design; integrated circuit interconnections; parallel architectures; DS-CDMA wired bus; I/O pin count; bus architecture; direct sequence code division multiple access; gigascale integrated systems; interconnection topology; parallel processing system LSIs; Circuit noise; Clocks; Integrated circuit interconnections; Large scale integration; Modulation coding; Multiaccess communication; Parallel processing; Radio transmitters; Topology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839820
