Author :
Kuge, S. ; Kato, T. ; Furutani, K. ; Kikuda, S. ; Mitsui, K. ; Hamamoto, T. ; Setogawa, J. ; Hamade, K. ; Komiya, Y. ; Kawasaki, S. ; Kono, T. ; Amano, T. ; Kubo, T. ; Haraguchi, M. ; Kawaguchi, Z. ; Nakaoka, Y. ; Akiyama, M. ; Konishi, Y. ; Ozaki, H.
Author_Institution :
ULSI Dev. Centre, Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A delay-locked loop (DLL) must have a large delay line to work over a wide range of frequency. This makes the layout area larger. A hierarchy delay line solves this problem. But coarse and fine delay changing at the same time causes jitter. This DLL and voltage down converter (VDC) avoids the jitter problem.
Keywords :
DRAM chips; delay lock loops; memory architecture; phase detectors; timing jitter; 0.18 micron; 256 Mbit; DLL replica; double-data-rate-SDRAM; hierarchy delay line; jitter problem; low-cost post-mold-tuning method; phase detector; replica tuning; voltage down converter; Circuit optimization; Circuit testing; Clocks; Counting circuits; Delay lines; Fuses; Jitter; Laser tuning; Timing; Voltage;
