A 500 Mb/s/pin quadruple data rate SDRAM interface using a skew cancellation technique

The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved accordingly in spite of quadrupled increase in the memory density every three years. This imbalance requires memory systems to use a wide data-bus and/or a high-speed I/O interface to increase access speed. Increasing access speed with a wide data-bus is studied, but is practically limited by memory pin counts. Alternatively, Rambus DRAM (RDRAM) achieves access speed up to 800 MB/s in a well-controlled printed circuit board (PCB) environment by adopting a high-speed I/O interface. Low cost systems use synchronous DRAM (SDRAM) interface because they cannot afford a high-cost PCB. This system limits memory access speed to the system clock speed, which is commonly less than 100 MHz. Double data rate (DDR) SDRAM, is twice as fast as SDRAM memory access by taking both rising and falling edges of the system clock, while keeping the SDRAM interface. To deal with clock skew, the DDR SDRAM provides an extra strobe signal for the receiving end.