Title :
UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor
Author :
Lauterbach, G. ; Greenley, D. ; Ahmed, S. ; Boffey, M. ; Chamdani, J. ; Si-En Chang ; Chen, D. ; Yu Fang ; Holdbrook, K. ; Hsieh, M. ; Keish, B. ; Melanson, R. ; Narasimhaiah, C. ; Petolino, J. ; Tung Pham ; Le Quach ; Kit Tam ; Duong Tong ; Liuxi Yang ;
Author_Institution :
Sun Microsyst., Palo Alto, CA, USA
Abstract :
UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.
Keywords :
cache storage; microprocessor chips; parallel architectures; pipeline processing; 1.5 V; 64 bit; 800 MHz; UltraSPARC-III; associative caches; associative write; data prefetch cache; enterprise server platforms; four-instruction-issue superscalar microprocessor; high-performance desktop workstation; off-chip unified second-level cache; on-chip caches; on-chip tag array; pipeline diagram; seven-layer metal process; third-generation SPARC microprocessor; work group server; Clocks; Delay; Graphics; Microprocessors; Pipelines; SDRAM; Scalability; Sun; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839837
