A 660 MHz self-resetting 8 port, 32/spl times/64 bits register file and latch in 0.25 /spl mu/m SOI technology

Design issues associated with dynamic circuits such as collisions, pulse widening, and noise margins are anticipated to be very sensitive to SOI process and device conditions. Multi-port dynamic register files and latches are important elements in current microprocessors. We designed such a register file and latch for bulk silicon technology, but it can be fabricated in SOI technology without any body contacts. The register file and latch function at frequencies higher than 660 MHz. The salient features are low voltage operability, fully collision-free operation and minimum noise. A robust design is demonstrated with respect to input pulse width variation and skew margins. Charge sharing noise and noise due to leakage coupling and power supply variations are controlled using half latches on the dynamic nodes and by properly optimizing circuits and layouts.