Title :
The first IA-64 microprocessor: a design for highly-parallel execution
Author :
Singer, G. ; Rusu, S.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The first implementation of the IA-64 architecture achieves high performance by implementing a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. The processor contains 25.4 M transistors. The chip is fabricated in a 0.18 /spl mu/m CMOS process with 6 metal layers and packaged in a 1012-pad organic land grid array using C4 (flip-chip) assembly technology.
Keywords :
CMOS digital integrated circuits; microprocessor chips; parallel architectures; 0.18 micron; C4 flip-chip assembly; CMOS chip; IA-64 architecture; highly parallel execution; microprocessor; organic land grid array package; Capacitance; Circuits; Clocks; Computer aided instruction; Concurrent computing; Crosstalk; Frequency; Hardware; Microprocessors; Registers;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839843
