Improving the accuracy of on-chip parasitic extraction

Author

Huang, Ching-Chao ; Oh, Kyung Suk ; Wang, Shun-Lien ; Panchapakesan, Sridhar

Author_Institution

Technol. Modeling Assoc. Inc., Sunnyvale, CA, USA

fYear

1997

fDate

27-29 Oct. 1997

Firstpage

42

Lastpage

45

Abstract

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.

Keywords

Monte Carlo methods; VLSI; capacitance; circuit analysis computing; circuit layout CAD; integrated circuit design; knowledge based systems; parameter estimation; 3D Monte-Carlo field solver; capacitance models; field-solver simulations; full-chip parasitics; nonlinear regression; on-chip parasitic extraction; rule-based layout parameter extraction; Conductors; Data mining; Delay; Finite difference methods; Inductance; Parameter extraction; Parasitic capacitance; Time to market; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on

Conference_Location

Austin, TX

Print_ISBN

0-7803-8649-3

Type

conf

DOI

10.1109/EPEP.1997.634035

Filename

634035