Title :
3D Global Interconnect Parameter ExtractoR for full-chip global critical path analysis
Author :
Oh, S.Y. ; Okasaki, K. ; Moll, J. ; Nakagawa, O.S. ; Chang, N.
Author_Institution :
ULSI Res. Lab., Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect parameters (R,C) of a typical global interconnect within several minutes per net on a HP 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.
Keywords :
VLSI; capacitance; circuit layout CAD; critical path analysis; integrated circuit design; integrated circuit interconnections; parameter estimation; 3D global interconnect parameter extractor; HP 9000/755 workstation; IC interconnects; VLSI; capacitance; full-chip global critical path analysis; interconnect parameters; Capacitance; Clocks; Frequency; Geometry; Integrated circuit interconnections; Libraries; Microprocessors; Numerical simulation; Routing; Solid modeling;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-8649-3
DOI :
10.1109/EPEP.1997.634036
