Title :
A hierarchical power supply distribution model for full-chip switching noise analysis
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.
Keywords :
VLSI; integrated circuit modelling; integrated circuit noise; power supply circuits; switching circuits; SCM power supply distribution; VLSI design; distributed switching circuit model; full-chip switching noise analysis; hierarchical on-chip power bus model; hot spots; Artificial intelligence; Circuit noise; Crosstalk; Noise reduction; Packaging; Power supplies; Signal design; Switching circuits; Threshold voltage; Very large scale integration;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-8649-3
DOI :
10.1109/EPEP.1997.634039
