Title :
A 16b 65 MSps pipeline ADC core with 230 fs clock jitter in 3.3 V SiGe BiCMOS: from simulation to silicon
Author :
Zanchi, Alfio ; Tsay, F. ; Papantonopoulos, Ioannis N.
Author_Institution :
High-Speed Data Converters, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This work introduces key simulation techniques enabling the design of a 16b 65 MSps pipeline ADC in 0.4 μm, 45 GHz-fT SiGe BiCMOS. A complete methodology for INL investigation with SPICE leads to understand the distortion introduced by Track/Hold as well as quantizer at 3.3 V supply and high input range (4Vpp). Simulations of aperture uncertainty are presented that match the measured 230 fs jitter, yielding 74.5 dBFS SNR at 150 MHz input. The test chip delivers 78.3 dBFS SNR, 88 dBc SFDR at 65 MSps/1 MHz with 970 mW power consumption.
Keywords :
BiCMOS digital integrated circuits; Ge-Si alloys; SPICE; analogue-digital conversion; circuit simulation; digital-analogue conversion; high-speed integrated circuits; integrated circuit design; jitter; 0.4 micron; 150 MHz; 16 bit; 230 fs; 3.3 V; 45 GHz; 65 MSps pipeline ADC core; 65 MSps pipeline ADC design; 970 mW; A/D conversion; D/A conversion; INL investigation; SPICE; SiGe; SiGe BiCMOS; aperture uncertainty; clock jitter; power consumption; silicon; simulation techniques; test chip; Analog-digital conversion; BiCMOS digital integrated circuits; Digital-analog conversion; Germanium alloys; Integrated circuit design; Jitter; SPICE; Silicon alloys;
Conference_Titel :
Implementation of High Performance Circuits, 2004. (DCAS-04). Proceedings of the 2004 IEEE Dallas/CAS Workshop
Print_ISBN :
0-7803-8713-9
DOI :
10.1109/DCAS.2004.1360455
