DocumentCode
1969490
Title
PLED-planar localised electron devices
Author
Nakazato, K. ; Piotrowicz, P.J.A. ; Hasko, D.G. ; Ahmed, H. ; Itoh, K.
Author_Institution
Cavendish Lab., Hitachi Europe Ltd, UK
fYear
1997
fDate
10-10 Dec. 1997
Firstpage
179
Lastpage
182
Abstract
In a Planar Localised Electron Device (PLED) electrons are localised in-plane and controlled by an external potential. It is the basis of a non-volatile, high-speed, stacked random access memory (RAM) cell which has very low power consumption. It operates at room temperature, and it can be fabricated by established silicon processing.
Keywords
DRAM chips; nitridation; single electron transistors; tunnel transistors; 298 K; PLED; external potential; high-speed memories; nitridation; nonvolatile stacked RAM; planar localised electron devices; power consumption; room temperature operation; single electron devices; Electrodes; Electron devices; Fabrication; Laboratories; Leakage current; Magnetic tunneling; Random access memory; Silicon; Single electron devices; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-4100-7
Type
conf
DOI
10.1109/IEDM.1997.650303
Filename
650303
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