Title :
Yield improvement and repair trade-off for large embedded memories
Author_Institution :
Logic Vision Inc., San Jose, CA, USA
Abstract :
In this paper, we give an overview of the trade-off to improve yield and optimize silicon manufacturing cost. The specific technology focus is on large embedded memories in complex ASIC or system-on-chip designs. Embedded capabilities for test, redundancy analysis and repair are shown as design-for-manufacturability features needed for large embedded memories in VDSM design
Keywords :
application specific integrated circuits; built-in self test; design for manufacture; design for testability; integrated circuit testing; integrated circuit yield; integrated memory circuits; redundancy; BIST; DFM features; SOC designs; built-in redundancy analysis; built-in self-repair; complex ASIC designs; design-for-manufacturability features; large embedded memories; manufacturing cost optimisation; redundancy analysis; system-on-chip designs; yield improvement; Application specific integrated circuits; Circuit testing; Logic testing; Manufacturing processes; Random access memory; Redundancy; Semiconductor device manufacture; Silicon; System testing; System-on-a-chip;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840018
