Title :
Transaction level modeling: flows and use models
Author_Institution :
Xilinx Res. Labs., San Jose, CA, USA
Abstract :
Transaction-level models (TLMs) address the problems of designing increasingly complex systems by raising the level of design abstraction above RTL. However, TLM terminology is presently a subject of contentious debate and a coherent set of TLM use-models have not been proposed. In This work we propose a variety of TLM use-models that reveal paths through the TLM abstraction levels for various types of system. We begin by stating the abstraction levels that comprise ´transaction-level´ and identify roles and responsibilities that apply within the use-models. We then take each use-model and discuss the type of system it applies to, the TLM abstraction levels it supports, and the design activites applied at those levels. We also consider the distribution of modeling effort between the various design roles and apply that to descriptions of various use-model design flows.
Keywords :
formal verification; large-scale systems; modelling; transaction processing; TLM abstraction levels; TLM use-models; complex systems; design abstraction; system design; system verification; transaction level modeling; use-model design flows; Costs; Data structures; Design methodology; Logic design; Market opportunities; Partitioning algorithms; Permission; Standardization; Terminology; Timing;
Conference_Titel :
Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. International Conference on
Print_ISBN :
1-58113-937-3
DOI :
10.1109/CODESS.2004.240821