DocumentCode
1970084
Title
Analysis and minimization of test time in a combined BIST and external test approach
Author
Sugihara, Makoto ; Date, Hiroshi ; Yasuura, Hiroto
Author_Institution
Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
fYear
2000
fDate
2000
Firstpage
134
Lastpage
140
Abstract
In this paper, an, analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test approach can achieve shorter testing time than both external test and BIST in many situations. An efficient test time minimization algorithm for CBET-based LSIs is also proposed. It uses several characteristics of CBET test approach derived by the analysis to reduce computation time to find the optimum test sets. The algorithm helps designers to save their precious design time
Keywords
built-in self test; integrated circuit testing; large scale integration; logic testing; minimisation; BIST; CBET; LSI; external test; logic test; test time minimization algorithm; Algorithm design and analysis; Built-in self-test; Circuit testing; Cities and towns; Computer science; Information technology; Minimization methods; Processor scheduling; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location
Paris
Print_ISBN
0-7695-0537-6
Type
conf
DOI
10.1109/DATE.2000.840029
Filename
840029
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