Defect free deep trench isolation for high voltage bipolar application on SOI wafer

Author

Yindepol, W. ; Bashir, Rumaan ; McGregor, J.M. ; Brown, K.C. ; De Wolf, Ingrid ; De Santis, J. ; Ahmed, A.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1998

fDate

5-8 Oct. 1998

Firstpage

151

Lastpage

152

Abstract

The trench architecture and process flow for a 170 V complementary bipolar technology with trench isolation and bonded wafer substrates is described. Electrical and material (micro-Raman) characterization is used to show that the process architecture and optimized process flow results in defect free silicon device regions.

Keywords

Raman spectra; bipolar integrated circuits; integrated circuit testing; isolation technology; optimisation; power integrated circuits; silicon-on-insulator; wafer bonding; 170 V; SOI wafer; Si-SiO/sub 2/; bonded wafer substrates; complementary bipolar technology; defect free deep trench isolation; defect free silicon device regions; electrical characterization; high voltage bipolar application; material characterization; micro-Raman characterization; optimized process flow; process architecture; process flow; trench architecture; trench isolation; Capacitance; Circuit testing; Dielectric devices; Dielectric substrates; Etching; Geometry; Implants; Materials testing; Voltage; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1998. Proceedings., 1998 IEEE International

Conference_Location

Stuart, FL, USA

ISSN

1078-621X

Print_ISBN

0-7803-4500-2

Type

conf

DOI

10.1109/SOI.1998.723156

Filename

723156