Title :
Smart antenna receiver based on a single chip solution for GSM/DCS baseband processing
Author :
Girola, U. ; Picciriello, A. ; Vincenzoni, D.
Author_Institution :
Siemens ICN SpA, Milan, Italy
Abstract :
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (lSI) reduction in GSM/DCS systems. The temporal channel for the Viterbi receiver and the beamformer weights for the CCI rejection are estimated jointly by optimizing a suitable cost function for separable space-time channels. Taking into account present day integration capabilities provided by FPGA (Field Programmable Gate Array), the feasibility is demonstrated of a single chip JSTE solution based on a three processor architecture for carrier beamforming, equalization and demodulation
Keywords :
Viterbi detection; adaptive antenna arrays; adaptive equalisers; array signal processing; cellular radio; cochannel interference; demodulation; digital signal processing chips; field programmable gate arrays; interference suppression; intersymbol interference; parallel architectures; radio receivers; space-time adaptive processing; telecommunication computing; CCI rejection; DCS baseband processing; FPGA; GSM baseband processing; JSTE algorithm; JSTE receiver; Viterbi receiver; beamformer weights; carrier beamforming; co-channel interference reduction; cost function; demodulation; equalization; intersymbol interference reduction; lSI reduction; separable space-time channels; single chip implementation; smart antenna receiver; space-time algorithm; three processor architecture; Array signal processing; Cost function; Distributed control; Field programmable gate arrays; GSM; Interchannel interference; Intersymbol interference; Radiofrequency interference; Receiving antennas; Viterbi algorithm;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840036
