Title :
Logical Effort using a Novel Discrete Particle Swarm Optimization algorithm
Author :
Hassan, H.A. ; Yassin, I.M. ; Halim, A.K. ; Zabidi, A. ; Majid, Z.A. ; Abidin, H.Z.
Author_Institution :
Fac. of Electr. Eng., Univ. Teknol. Mara, Shah Alam
Abstract :
Designers often need to choose the gate sizes for logic circuit designs to estimate the delay of the circuit. Simulation and timing analysis are poor tools for this task because they cannot be modified for better results. Hence, the method of Logical Effort (LE) provides a simple method to overcome these design problems. We apply a novel Discrete Particle Swarm Optimization algorithm (DPSO) to solve the LE problem for electronic circuits. The method uses the rescaling function commonly used to scale datasets in neural networks to convert continuous-valued PSO values into discrete values. The proposed algorithm was successfully applied on a three-stage NAND gate circuit, and has been shown to work well, with 100% accuracy in all test runs.
Keywords :
delay estimation; logic circuits; logic design; particle swarm optimisation; circuit delay estimation; discrete particle swarm optimization algorithm; logic circuit design; logical effort method; rescaling function; three-stage NAND gate circuit; Algorithm design and analysis; Circuit testing; Delay estimation; Logic circuits; Logic design; Logic gates; Particle swarm optimization; Signal design; Signal processing algorithms; Timing;
Conference_Titel :
Signal Processing & Its Applications, 2009. CSPA 2009. 5th International Colloquium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-4151-8
Electronic_ISBN :
978-1-4244-4152-5
DOI :
10.1109/CSPA.2009.5069266