An on chip ADC test structure

In this paper; a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a test input signal. A specific range of this signal is divided into 2ⁿ⁺¹ segments, with each segment corresponding to one output combination of an n+1-bit counter; where n is the number of bits of the ADCs under test. The testing process is done with digital data processing by comparing the outputs of ADCs under test with the outputs of the n+1 bit counter. Simple structure, low area overhead, and high speed are the advantages of the proposed test structure