Side channel resistance quantification and verification

In this paper, a formal method for quantifying the side channel resistance based on a statistical approach is developed and a formal CAD method for verifying the side channel resistance of a circuit design is presented. Our analysis indicates that designs which have small means for the difference in power consumption between key bits and high standard deviations for the difference can achieve higher security. Our analytical results for quantifying side channel resistance indicate that it is not feasible to achieve 280 security against side channel attacks with low standard deviation or with large means in the difference between key bit runs. Additionally, our analytical results for a preliminary CAD approach to detecting side channel leakage show that significant computing resources are required to gain enough statistics on the power consumption of a circuit to make reasonable approximations about the system´s side channel resistance performance prior to implementation when the side channel attacks are unknown; however, our results indicate that it is feasible to detect individual side channel vulnerabilities when the side channel attacks are known.