New polysilicon disposable sidewall process for sub-50 nm CMOS

Author

Lee, K.L. ; Boyd, D. ; Brancaccio, J. ; Bucchignano, J. ; Cai, J. ; Chan, K. ; Hanafi, H. ; Kozlowski, P. ; Miller, R. ; Roy, R. ; Shi, L. ; Sikorski, E. ; Surendra, M. ; Wind, S. ; Yang, Q. ; Yoon, J. ; Yu, C. ; Zhang, Y. ; Taur, Y.

Author_Institution

IBM Thomas J. Watson Research Center, Yorktown Heights, USA

fYear

2001

fDate

11-13 September 2001

Firstpage

159

Lastpage

162

Keywords

Annealing; Boron; CMOS process; Chemical vapor deposition; Doping; Etching; Implants; Microelectronics; Strips;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2001. Proceeding of the 31st European

Print_ISBN

2-914601-01-8

Type

DOI

10.1109/ESSDERC.2001.195225

Filename

1506607

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