A reconfigurable approach to hardware implementation of neural networks

Hardware inefficiency of neural synapse multiplication has placed an upper limit on the neural network size that can be implemented on a single FPGA. In this paper, we make use of distributed arithmetic and internal lookup tables of FPGA structures to improve the efficiency of synapse multiplication. We propose a weight clustering optimization method to further reduce area requirements of the target hardware. Applying our proposed method to a sample neuron, we were able to reduce the hardware requirements of synapse multiplier by 30%. Our parameterized approach can be utilized for automation of neural network synthesis onto FPGA devices.