Title :
The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance
Author :
Mohapatra, Nihar R. ; Desai, Madhav P. ; Narendra, Siva G. ; Rao, V. Ramgopal
Author_Institution :
Indian Institute of Technology, Bombay, India
fDate :
11-13 September 2001
Keywords :
CMOS technology; Circuit noise; Circuit optimization; Circuit simulation; Degradation; Dielectric devices; Medical simulation; Parasitic capacitance; Permittivity; Tunneling;
Conference_Titel :
Solid-State Device Research Conference, 2001. Proceeding of the 31st European
Print_ISBN :
2-914601-01-8
DOI :
10.1109/ESSDERC.2001.195245
