Inductance aware performance and reliability analysis of high performance integrated circuits

Author

Roy, Abinash ; Xu, Jingye ; Chowdhury, Masud H.

Author_Institution

Univ. of Illinois at Chicago, Chicago

fYear

2007

fDate

17-20 May 2007

Firstpage

91

Lastpage

95

Abstract

This paper presents an analysis of the positive and negative impacts of on-chip inductance. It has been illustrated that inductance can be exploited to improve some aspects of the performance of high speed integrated circuits. On the other hand, voltage overshoots due to inductance can increase the effective gate voltage stress so high that it may cause serious concern for gate oxide reliability in current ultra-thin (1-5 nm) MOS gate dielectrics since failure rate is exponentially dependent on the effective voltage stress. It is observed that failure probability of device oxide may be increased by more than double for 10% change in voltage overshoot.

Keywords

CMOS integrated circuits; integrated circuit reliability; high performance integrated circuits; high speed integrated circuits; inductance aware performance; on-chip inductance; reliability analysis; Capacitance; Circuit analysis; Dielectrics; Inductance; Integrated circuit interconnections; Integrated circuit reliability; Performance analysis; RLC circuits; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electro/Information Technology, 2007 IEEE International Conference on

Conference_Location

Chicago, IL

Print_ISBN

978-1-4244-0941-9

Electronic_ISBN

978-1-4244-0941-9

Type

conf

DOI

10.1109/EIT.2007.4374478

Filename

4374478