RF/wireless interconnects in future on-chip and board-level clock distribution network

With operating frequencies in GHz regime, problems associated with digital systems in terms of clock skew, jitter, power consumption, bit error rate (BER), and signal integrity are becoming critical in on-chip/off-chip clock distribution networks using conventional copper interconnect technology, which has emerged as a performance limiter for current and future VLSI circuits. In order to mitigate these rising problems and maintain the continuous improvement of high speed integrated circuits, different alternative approaches such as 3-D interconnect, RF/wireless interconnect and optical interconnect have currently been investigated. This paper presents an overview of the limitations of conventional clock distribution networks, and investigates the feasibility and challenges of adopting RF/wireless interconnects in future on-chip and board-level clock distribution networks. Exploratory research results show that these new interconnect technologies will offer desired performances for future high speed clock distribution network operating in multi GHz frequencies if design and integration challenges can be resolved. Based on the survey among the available alternatives, RF/wireless interconnect seems to be the most viable candidate to replace copper interconnect in near future technology nodes (up to 20 GHz).