Title :
A new IEEE 1149.1 boundary scan design for the detection of delay defects
Author :
Park, Sungju ; Kim, Taehyung
Author_Institution :
Dept. of Comput. Sci. & Eng., Hanyang Univ., Ansan, South Korea
Abstract :
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores cannot be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore, 2log(N+2) interconnect test patterns are proposed for both static and delay testing
Keywords :
IEEE standards; automatic testing; boundary scan testing; delays; design for testability; integrated circuit interconnections; integrated circuit testing; logic testing; DFT technique; I/O pads; IEEE 1149.1 boundary scan design; TAP controller modification; delay defects detection; delay testing; design technique; interconnect test patterns; interconnections; static testing; Circuit faults; Circuit testing; Computer science; Delay; Electrical capacitance tomography; Integrated circuit interconnections; Ores; Packaging; Registers; System testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840311
