An ultra-low-power self-biased current reference

This paper presents the design of an ultra-low-power self-biased 400 pA current source. An efficient design methodology has resulted in a cell area around 0.045 mm² (0.027 mm²) in the AMIS 1.5 μm (TSMC 0.35 μm) CMOS technology and power consumption around 2 nW for 1.2 V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1 V with a good regulation (<4%/V variation of the supply voltage in a 0.35 μm technology). This current source is suitable for very-low-power applications.