A simultaneous switching noise analysis of a high speed memory module including the test environments and system-level models

As memory module products become more byte-wide and operate at higher speeds, more of the simultaneous switching noise (SSN) is observed. This paper presents SSN analysis results of high speed memory modules considering the power/ground planes and various interconnects of a test environment and computer system. Using the proposed model, highly accurate simulation results are obtained. Furthermore, we analyze the effect of SSN on the clock jitter and RAS Vil margin. The same model is also used to observe the effect of the decoupling capacitors on SSN. Based on our analysis, memory modules can be redesigned to increase the reliability.