Title :
Analog circuit layout with optimized performance
Author :
Hong, Seong K. ; Allen, Phillip E.
Author_Institution :
Dept. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
An approach for developing a component-level use of a layout compiler which results in a circuit layout along with a user-specified performance is described. The methodology is based on sensitivities of the circuit performance with respect to layout interconnect parasitics and recognition rules of various configurations and topologies. The parasitic effects, which are important from an analog layout point of view, are examined as the methods used to minimize them
Keywords :
analogue circuits; circuit layout CAD; integrated circuit technology; linear integrated circuits; analogue circuit layout; component-level use; layout compiler; layout interconnect parasitics; parasitic effects; recognition rules; user-specified performance; Analog circuits; Circuit optimization; Circuit topology; Data structures; Digital circuits; Integrated circuit interconnections; Routing; SPICE; Sensitivity analysis; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101917
