CMOS IC reliability assesment for government applications

I will present an overview of the work my organization is doing in support of the DARPA “IRIS” Program. Our work: focuses on developing the technology to predict the long-term reliability of COTS Ics (both Digital and Analog Mixed Signal) from a very limited sample set (≤ 10 chips). We focus on wear-out or “aging” related reliability effects including negative-bias-temperature-instability (NBTI), time-dependent-dielectric-breakdown (TDDB), and hot carrier (HC). A three-prong approach is used in our prediction methodology: 1) building better wear-out models for select CMOS technologies using experimental reliability data, 2) building custom reliability circuit simulation tools to apply these models to IC test articles, 3) Developing “in-situ” testing methods to acquire reliability data from COTs Ics (without the use of custom reliability test circuits). The ultimate goal is the development of efficient methods for evaluating mean-time-to-failure of COTs Ics from very limited sample sets.