Reliability testing and test structure design in an age of increasing variability

Two challenges of semiconductor device scaling are: 1) process complexity increases with each generation 2) variability increases with device scaling. The impact of 1) is clear to anyone involved in early process development, when apparently trivial changes in process for high-kmetal gate stacks can lead to significant changes in such reliability characteristics as BTI time slope, magnitude, and recovery, all often treated as universals in reliability literature. Almost by definition 2) could be considered most challenging in reliability relative to other areas of semiconductor engineering because in practice semiconductor reliability is the study of spatially and temporally rare events often involving one or several atoms. The two challenges are intimately linked because when advanced process node features such as stress liners, stress memorization and raised source/drains play a role in device performance, the channellength/width become only one piece of the layout induced variability. These challenges drive the need for faster reliability measurements done in higher volume. Testing can be done on individual devices with several SMUs, through simplified decoder structures with thousands of devices, to full product level using very expensive APGs. We discuss some of the engineering and (necessarily) economic choices that drive the techniques and structures used for electrical measurements made at each of these levels.