Title :
A reliable TDDB lifetime Projection model for advanced gate stack
Author :
Chen, S.C. ; Chen, C.L. ; Lee, Young-Hyun ; Chang, S.W. ; Shih, J.R. ; Lee, Yong Wook ; Maji, D. ; Wu, Kaijie
Author_Institution :
Technol. Quality & Reliability Div., Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
In this paper, a reliable TDDB lifetime projection by modeling the gate leakage current degradation is proposed. The validity of model is demonstrated by the good agreements with the experimental results. The two-stage Ig degradation and voltage-dependent Weibull slope are explained through the associated trap generation during the TDDB stress. Based on this model., accurate TDDB lifetime prediction can be achieved for HK/IL gate stack.
Keywords :
MOSFET; leakage currents; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; HK-IL gate stack; TDDB stress; gate leakage current degradation; nMOSFETs; reliable TDDB lifetime projection model; time dependent dielectric breakdown; trap generation; voltage-dependent Weibull slope; Data models; Degradation; Dielectrics; Electron traps; Logic gates; Reliability; Stress; HK/IL; TDDB; Weibull slope; lifetime model;
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2013 IEEE International
Conference_Location :
South Lake Tahoe, CA
Print_ISBN :
978-1-4799-0350-4
DOI :
10.1109/IIRW.2013.6804169
