A new partitioning method for LUT-based FPGAS

In this paper, the author proposes a new partitioning method for look-up table (LUT)-based field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, partitioning a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. The typical EDA tools deal mainly with AND/OR expressions and therefore are quite inefficient for the parity prediction functions since parity prediction function is inherently AND/XOR in nature. The author examines the application of the Davio´s expansion theorem in the decomposition of the AND/XOR expressions. The MCNC benchmark circuits are used here to demonstrate the effectiveness of the proposed techniques. The proposed Davio approach takes only on average 2.75 extra CLBs or 20% of the original area and maximum combinational path delay is reduced by 56.7% compared to the typical method.