A low-power, high-speed 4-bit GaAs ADC and 5-bit DAC

Author

Naber, J.F. ; Singh, H.P. ; Sadler, R.A. ; Milan, J.M.

Author_Institution

ITT Gallium Arsenide Technol. Center, Roanoke, VA, USA

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

333

Lastpage

336

Abstract

A 4-b flash analog-to-digital converter (ADC) and 5-b digital-to-analog converter (DAC) have been designed and fabricated in gallium arsenide using a 0.7- mu m MESFET self-aligned gate process. The ADC operates at a 1-GHz sampling rate with a chip power dissipation of only 140 mW, while the DAC consumes only 85 mW of power at a 1-GHz sampling rate. To overcome the material limiting deficiencies of the MESFET in higher-resolution flash ADCS, a subranging technique can be implemented using two ADCs and a DAC. This technique places the resolution limitation primarily on the DAC.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; analogue-digital conversion; digital-analogue conversion; field effect integrated circuits; gallium arsenide; 0.7 micron; 140 mW; 85 mW; GaAs; MESFET self-aligned gate process; chip power dissipation; flash analog-to-digital converter; resolution limitation; sampling rate; subranging technique; Circuit testing; Clocks; Decoding; FETs; Gallium arsenide; Latches; Logic; Microwave circuits; Positron emission tomography; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69355

Filename

69355