A reconfigurable digital multiplier architecture

There has been recent awareness of the drastic effects of interconnect delay in VLSI implementations, and several investigations focused on this problem have been linked directly to multiplier structures. The tree, or column compression techniques, used for partial product reduction have the severe impediment of highly irregular interconnections. A digital multiplier architecture is presented in this paper that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration. Regulated by a 2-bit control signal, the multiplier provides optimal circuitry for both single and double precision arithmetic, as well as fault tolerant and dual throughput single precision operation. Moreover, dynamic power management techniques allow for 75% power reduction in single precision mode, and 50% power reduction for SIMD applications.