A novel soft error immunity SRAM cell

Author

Xuemei Liu ; Liyang Pan ; Xin Zhao ; Fengying Qiao ; Dong Wu ; Jun Xu

Author_Institution

Inst. of Microelectron. Tsinghua Univ., Beijing, China

fYear

2013

fDate

13-17 Oct. 2013

Firstpage

173

Lastpage

176

Abstract

The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.

Keywords

CMOS memory circuits; SPICE; SRAM chips; circuit simulation; radiation hardening (electronics); technology CAD (electronics); 3D technology computer-aided design simulation; CMOS process; SPICE simulation; TCAD simulation; process variation; read state; size 65 nm; soft error immunity SRAM cell; soft error upset; MOS devices; Robustness; SRAM cells; Solid modeling; Standards; Transistors; SRAM; soft error immunity (SEI); soft error upset (SEU);

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2013 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

978-1-4799-0350-4

Type

conf

DOI

10.1109/IIRW.2013.6804187

Filename

6804187