Using safe operation regions to assess the error probability of logic circuits due to process variations

Author

Khalid, Usman ; Mastrandrea, Antonio ; Olivieri, Mauro

Author_Institution

Dept. of Inf., Electron. & Telecommun. Eng., Sapienza Univ. of Rome, Rome, Italy

fYear

2013

fDate

13-17 Oct. 2013

Firstpage

177

Lastpage

180

Abstract

Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.

Keywords

CMOS digital integrated circuits; Monte Carlo methods; circuit simulation; error statistics; integrated circuit noise; integrated logic circuits; CMOS technology; Monte Carlo evaluation; digital circuits; error probability; logic circuits; process variations; safe operation region; voltage noise; Integrated circuit modeling; Inverters; Monte Carlo methods; SPICE; Semiconductor device modeling; Standards; Threshold voltage; Process variations; digital VLSI circuits; nano-CMOS circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2013 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

978-1-4799-0350-4

Type

conf

DOI

10.1109/IIRW.2013.6804188

Filename

6804188