A study on the VLSI implementation of ECC for embedded DRAM

Author

Gao, W. ; Simmons, S.

Author_Institution

Dept. of Electr. & Comput. Eng., Queen´´s Univ., Canada

Volume

1

fYear

2003

fDate

4-7 May 2003

Firstpage

203

Abstract

ECC circuitry is an effective on-line method for increasing the reliability and fault tolerance of high density DRAM. Code length, code type and implementation method affect delay and area penalty due to ECC. Four SEC-DED Hsiao codes: (39,32), (72,64), (137,128) and (266,256), are investigated in this paper. We look at the effect of word length on P(error), and compare XOR-tree based and LUT-based implementations. Simulation results show that an LUT structure outperforms the XOR-tree structure in error-correction speed in most cases, although it usually generates a larger area penalty. Our results can be used as a guide for selecting the proper code and implementation method for use in error- corrected DRAM.

Keywords

DRAM chips; VLSI; error correction codes; error detection; fault tolerance; table lookup; Code length; ECC circuitry; SEC-DED Hsiao codes; VLSI implementation; XOR-tree structure; code type; delay; dynamic random access memory; embedded DRAM; error-correction speed; fault tolerance; look up table; very large scale integration; word length; Delay; Driver circuits; Error correction codes; Fault tolerance; Hardware; Parity check codes; Random access memory; Space technology; Table lookup; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7781-8

Type

conf

DOI

10.1109/CCECE.2003.1226378

Filename

1226378