Reed-Solomon encoder & decoder design, simulation and synthesis

Author

Ardalan, Shahab ; Raahemifar, Kaamran ; Yuan, Fei ; Geurkov, Vadim

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada

Volume

1

fYear

2003

fDate

4-7 May 2003

Firstpage

255

Abstract

Truth of information in any communication system is very critical. Use of forward error correction (FEC) to lower the probability of error and increase transmission distance has become common. Reed-Solomon is a block FEC, capable of correcting multiple errors, specifically focusing on burst errors, making it widespread for storage devices, and wireless and mobile communication units. This paper presents an implementation of a (7,3) Reed-Solomon encoder-decoder using VHSIC hardware description language (HDL). The encoder downloaded into Altera MAX 7128 CPLD for functional and timing verification, and decoder is ready for fabrication.

Keywords

Reed-Solomon codes; codecs; decoding; error statistics; forward error correction; hardware description languages; Altera MAX 7128 CPLD; Reed-Solomon encoder-decoder; VHSIC hardware description language; burst errors; communication system; error probability; forward error correction; functional verification; mobile communication units; storage devices; timing verification; transmission distance; wireless communication units; Decoding; Error correction; Fabrication; Forward error correction; Hardware design languages; Mobile communication; Reed-Solomon codes; Timing; Very high speed integrated circuits; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7781-8

Type

conf

DOI

10.1109/CCECE.2003.1226390

Filename

1226390