An integrated patch-clamp amplifier for ultra-low current measurement on solid-state nanopore

Author

Jungsuk Kim ; Gang Wang ; Dunbar, W.B. ; Pedrotti, K.

Author_Institution

Electr. Eng., Univ. of Santa Cruz, Santa Cruz, CA, USA

fYear

2010

fDate

22-23 Nov. 2010

Firstpage

424

Lastpage

427

Abstract

In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pA_RMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm². This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.

Keywords

amplifiers; integrated low-noise patch-clamp amplifier; optimal feedback resistance; solid-state nanopore; trans-impedance amplifier; ultra-low current measurement; unity-gain buffer; voltage-gain amplifier; Bandwidth; CMOS integrated circuits; DNA; Gain; Nanobioscience; Noise; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2010 International

Conference_Location

Seoul

Print_ISBN

978-1-4244-8633-5

Type

conf

DOI

10.1109/SOCDC.2010.5682879

Filename

5682879