DocumentCode :
1974079
Title :
A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications
Author :
Lee, Kihoon ; Lee, Hanho
Author_Institution :
Dept. of Inf. & Commun. Eng., Inha Univ., Incheon, South Korea
fYear :
2010
fDate :
22-23 Nov. 2010
Firstpage :
428
Lastpage :
431
Abstract :
This paper presents a six-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed six-iteration concatenated BCH code structure with a block interleaving methods allows the decoder to achieve 9.19 dB net coding gain performance at 10-15 decoder output bit error rate to compensate for serious transmission quality degradation. Also, the proposed high-speed concatenated BCH decoder architecture was implemented to support 100 Gb/s data processing rate. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s long-haul optical communications.
Keywords :
BCH codes; concatenated codes; error statistics; optical communication; Bose-Chaudhuri-Hocquenghem code; bit error rate; bit rate 100 Gbit/s; block interleaving method; forward error correction; hardware architecture; high-performance concatenated BCH code; high-speed two-parallel decoder; optical communication; Bit error rate; Decoding; Error correction codes; Forward error correction; Optical fiber communication; Payloads; Redundancy; 100G; BCH; concatenated codes; net coding gain; optical communications;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
Type :
conf
DOI :
10.1109/SOCDC.2010.5682880
Filename :
5682880
Link To Document :
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