A VLSI architecture for a universal high-speed multirate FIR digital filter with selectable power-of-two decimation/interpolation ratios

A universal architecture for decimation/interpolation digital filtering applications is proposed for custom VLSI implementation to accommodate real-time signal processing at throughput rates in excess of 100 MHz. The main innovation of this architecture is that it allows a single chip to selectively perform decimation or interpolation filtering with selectable conversion ratios of 2¹,2²,. . .2 ^N. The key feature of the proposed architecture is that a single decimate/interpolate-by-two half-band digital filter is used as the computational engine, and the output samples are simply recycled through the same filter after each decimation/interpolation stage for further filtering. A delicate timing allocation scheme for this half-band filter to be shared among each decimation/interpolation stage plays a critical role in allowing the filter to have selectable conversion ratios and still accommodate throughput rates in excess of 100 MHz