Process algebraic specification of DI circuits

The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.