DocumentCode :
1974226
Title :
Process algebraic specification of DI circuits
Author :
Man, Ka Lok ; Asthana, Abhinav ; Hemangee, K.Kapoor ; Krilavicius, Tomas ; Chang, Jian
Author_Institution :
Dept. of Computer Science and Software Engineering, Xi´´an Jiaotong-Liverpool University (XJTLU)
fYear :
2010
fDate :
22-23 Nov. 2010
Firstpage :
396
Lastpage :
399
Abstract :
The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.
Keywords :
Integrated circuit modeling; Lead; Logic gates; Solid modeling; Synchronization; Variable speed drives;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Incheon, Korea (South)
Print_ISBN :
978-1-4244-8633-5
Type :
conf
DOI :
10.1109/SOCDC.2010.5682888
Filename :
5682888
Link To Document :
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