Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip

The growing size of Multi-Processor Systems-on-Chip (MP-SoC) calls for Networks-on-Chip (NoC) which scale with the increasing number of modules attached to them. Though current, 2D-mesh based NoCs scale linearly with the number of modules attached to them, their performance in terms of achievable throughput under typical traffic scenarios degrades. Clustered, hierarchical 2D-mesh NoCs may provide a solution to this problem by shortening the distance between two modules and adding more bandwidth. But it is merely researched what architectures with which parameters are suitable. In this paper we present and evaluate different realizations of clustered, hierarchical 2D-meshes, analyze their performance via cycle accurate simulations, determine their area consumption and derive recommendations which architecture is a suitable solution to the bandwidth degradation problem.